Design Rule Check Report
------------------------

Report File:        W:\Kallysta\Dev. Electronique\Carte Led15Proc\v2.0\Led15procv2 (PCB - Design Rule Check Report).txt
Report Written:     Thursday, October 20, 2016
Project Path:       W:\Kallysta\Dev. Electronique\Carte Led15Proc\v2.0\Led15procv2.prj
Design Path:        W:\Kallysta\Dev. Electronique\Carte Led15Proc\v2.0\Led15procv2.pcb
Design Title:       
Created:            28/07/2015 15:34:02
Last Saved:         20/10/2016 17:40:59
Editing Time:       1601 min
Units:              mm (precision 3)


Results
=======

Component to Component error (Cm-Cm) at (4.825 -205.405) on layer "[Top]".
    U1 - C6, Gap is 0.000.
Component to Component error (Cm-Cm) at (15.175 -196.210) on layer "[Top]".
    U1 - C4, Gap is 0.000.
Component to Component Error (Cm-Cm) between (0.460 -238.130) and (1.890 -238.130) on Layer "[Bottom]".
    U3 - R35, Gap is 0.000.
Component to Component Error (Cm-Cm) between (0.460 -239.770) and (1.890 -239.770) on Layer "[Bottom]".
    U3 - R36, Gap is 0.000.

Number of errors found : 4


Settings
========


Spacings

=========

Tracks        Yes
Pads and Vias Yes
Shapes        Yes
Text          Yes
Board         Yes
Drills        Yes
Components    Yes


Manufacturing

==============

Drill Breakout                  No
Drill Backoff                   No
Silkscreen Overlap              No
Copper Text In Board            Yes
Min Track Width                 Yes
Min Annular Ring                Yes
Min Paste Size                  No
Vias In Pads                    No
Unplated Vias                   Yes
Unplated Pads With Inner Tracks Yes


Nets

=====

Net Completion               Yes
Dangling Tracks              Yes
Net Track Length Differences No



End Of Report.