Design Rule Check Report ------------------------ Report File : \\psf\Home\Documents\Dev Electronique\Carte SAS6\v2.0\SAS6 (PCB - Design Rule Check Report).txt Report Written : Friday, March 07, 2014 Project Path : \\psf\Home\Documents\Dev Electronique\Carte SAS6\v2.0\SAS6.prj Design Path : \\psf\Home\Documents\Dev Electronique\Carte SAS6\v2.0\SAS6.pcb Design Title : Created : 07/11/2013 15:35:07 Last Saved : 07/03/2014 17:28:10 Editing Time : 3952 min Units : mm (precision 3) Results ======= Component to Component error (Cm-Cm) at (44.580 225.400) on layer "[Top]". J1 - TP1, Gap is 0.000. Component to Component error (Cm-Cm) at (44.580 22.400) on layer "[Top]". TP11 - J7, Gap is 0.000. Component to Component error (Cm-Cm) at (44.580 184.800) on layer "[Top]". J2 - TP3, Gap is 0.000. Component to Board error (Cm-B) at (11.250 117.500) on layer "[Top]". J11. Component to Board error (Cm-B) at (56.100 244.250) on layer "[Top]". J10. Component to Component error (Cm-Cm) at (62.800 241.570) on layer "[Top]". J10 - R22, Gap is 0.000. Component to Component error (Cm-Cm) at (62.730 240.675) on layer "[Top]". J10 - C41, Gap is 0.000. Component to Component error (Cm-Cm) at (44.580 144.200) on layer "[Top]". J3 - TP5, Gap is 0.000. Component to Component error (Cm-Cm) at (44.580 103.600) on layer "[Top]". TP7 - J4, Gap is 0.000. Component to Component error (Cm-Cm) at (44.580 63.000) on layer "[Top]". TP9 - J5, Gap is 0.000. Number of errors found : 10 Settings ======== Spacings ========= Tracks Yes Pads and Vias Yes Shapes Yes Text Yes Board Yes Drills Yes Components Yes Manufacturing ============== Drill Breakout Yes Drill Backoff No Silkscreen Overlap No Copper Text In Board Yes Min Track Width Yes Min Annular Ring Yes Min Paste Size No Vias In Pads Yes Unplated Vias Yes Unplated Pads With Inner Tracks Yes Nets ===== Net Completion Yes Dangling Tracks Yes Net Track Length Differences No End Of Report.